Field
The present disclosure relates generally to multi-pattern technology, and more particularly, to a multi-patterning compliance technique for determining and configuring group constraints of features within an integrated circuit (IC) layout.
Background
Continued demand for better performance and reduced power consumption of integrated circuits (ICs) has led to vast technological improvements in the semiconductor industry. The reduction of the size of components within the ICs, which allows for greater transistor density, faster speeds, and lower power consumption, is one such improvement.
Lithographic resolution, which governs the ability to project an accurate image of very small objects onto an IC substrate, is limited in part by the wavelength of light used during photolithography. This limit in lithographic resolution may be referred to as a “printable threshold.” Multi-patterning lithography (MPL) is one lithography technique that may be used to increase IC pattern density and overcome the limitations in lithographic resolution. MPL allows an IC layout to be decomposed into two or more colors (e.g., red, blue, yellow, etc.), such that features of one color are formed on one mask and features of another color are formed on another mask. By dividing features of an IC layout into multiple masks, it is possible to fabricate semiconductor devices with object sizes and spacing that are beyond the limits of lithographic resolution.
MPL, however, has many drawbacks, including very long color decomposition run times, decomposition problems that cannot be resolved or that never converge, color balance issues at chip level, and color conflict. Thus, the need arises for a solution that improves the color decomposition speed of MPL while avoiding color balance and conflict issues.